Dirty Little Secret: Schematics, PCB layout Assembly and Test

Schematics

In order to test both versions of the pedal, JFET and MOSFET, threee different PCBs are built:

• Base board including power supply, equalizer, conectors, potentiometers, switches and LED
• Mezzanine board with JFET DLS effect
• Mezzanine board with MOSFET DLS effect

Schematics first page is the base board that includes input stereo jack with ferrite filter, gain potentiometer, equalizer including capacitors, resistors and potentiometers, volumen potentiometer, output mono jack with ferrite filter, 3PDT switch for super lead / super bass option, +9 VDC input to +3.3 VDC regulator, effect on LED, connector to external 3PDT footswitch, 2 connectors to mezzanine board and the layout for an optional +1.65V mid-point voltage reference that is not used on this particular effect.

This baseboard can be used as a generic base for other effects.

Baseboard Schematics

Second page schematics contains MOSFET DLS effect
Three MOSFET amplifier stages are used. MOSFET has a biasing resistor network that includes a potentiometer to adjust biasing voltage on the MOSFET gate.
Gain is placed between the first and second stage.
Equalizer is placed between the second and third stage.
Third stage is just a buffer with no gain.

MOSFET DLS effect schematics

Third page schematics contains JFET DLS effect.
Three dual JFET amplifier stages are used. Top JFET has a biasing resistor network that includes a potentiometer to adjust biasing voltage on the top JFET gate.
Gain is placed between the first and second stage.
Equalizer is placed between the second and third stage.

JFET DLS effect schematics

The figure below shows top layer PCB layout . A panel has been made containing the three PCBs: baseboard, MOSFET mezzanine and JFET mezzanine. V-cut separation method is used.

Top layer PCB layout

The figure below shows bottom layer PCB layout. A panel has been made containing the three PCBs: baseboard, MOSFET mezzanine and JFET mezzanine. V-cut separation method is used.

Bottom layer PCB layout

Test

Both effects (JFET and MOSFET) have been tested using a 300mVpp 440 Hz sinewave signal on input.

JFET effect

The figure below shows the signal observed at the output of the first amplifier stage (Q1D1). A 1090mVpp sinewave is obtained which corresponds to a 11dB gain.

440Hw sinewave 1090mVpp signal at the first amplifier stage output (gain=3.6, 11dB) (q1d1)

The figure below shows the signal observed at the output of the second amplifier stage (TONEIN2). A 2110mVpp distorted sinewave is obtained which corresponds to a 17dB gain.

2110mVpp signal at the 2nd amplifier stage output (gain=7, 17dB) (tonein2)

The figure below shows the signal observed at the output of the equalizer and input to the 3rd amplifier stage (Q6G). A 850mVpp distorted sinewave is obtained which corresponds to a 9dB gain.

850mVpp signal at the equalizer output (gain=2.8, 9dB) (q6g)

The figure below shows the signal observed at the output of the 3rd amplifier stage output (FXOUT2). A 1730mVpp distorted sinewave is obtained which corresponds to a 15.2dB gain.

1730mVpp signal at the third stage amplifier output (gain=5.8, 15.2dB) (fxout2)

MOSFET effect

Three different biasing values have been used: low, mid, high.

The figure below shows the signal observed at the output of the first amplifier stage (Q1D) with low bias. A 1730mVpp distorted sinewave is obtained which corresponds to a 15dB gain.

1730 mVpp signal at the first amplifier stage output with low bias  (gain=5.8, 15dB) (q1d)

The figure below shows the signal observed at the output of the first amplifier stage (Q1D) with mid bias. A 3060mVpp distorted sinewave is obtained which corresponds to a 20dB gain.

3060 mVpp signal at the first amplifier stage output with mid bias  (gain=10.2, 20dB) (q1d)

The figure below shows the signal observed at the output of the first amplifier stage (Q1D) with high bias. A 700mVpp distorted sinewave is obtained which corresponds to a 7.4dB gain.

700 mVpp signal at the first amplifier stage output with high bias  (gain=2.3, 7.4dB) (q1d)

The figure below shows the signal observed at the output of the second amplifier stage (Q2D) with low bias. A 970mVpp distorted sinewave is obtained which corresponds to a 10.2dB gain.

970 mVpp signal at the second amplifier stage output with low bias  (gain=3.23, 10.2dB) (q2d)

The figure below shows the signal observed at the output of the second amplifier stage (Q2D) with mid bias. A 3220mVpp distorted sinewave is obtained which corresponds to a 20.6dB gain.

3220 mVpp signal at the second amplifier stage output with mid bias  (gain=10.7, 20.6dB) (q2d)

The figure below shows the signal observed at the output of the second amplifier stage (Q2D) with high bias. A 940mVpp distorted sinewave is obtained which corresponds to a 10dB gain.

940 mVpp signal at the second amplifier stage output with high bias  (gain=3.1, 10dB) (q2d)

The figure below shows the signal observed at the final buffer output (FXOUT1) with low bias. A 630mVpp distorted sinewave is obtained which corresponds to a 6.4dB gain.

630 mVpp signal at the final buffer output with low bias  (gain=2.1, 6.4dB) (fxout1)

The figure below shows the signal observed at the final buffer output (FXOUT1) with mid bias. A 2170mVpp distorted sinewave is obtained which corresponds to a 17.2dB gain.

2170 mVpp signal at the final buffer output with mid bias  (gain=7.2, 17.2dB) (fxout1)

The figure below shows the signal observed at the final buffer output (FXOUT1) with high bias. A 330mVpp distorted sinewave is obtained which corresponds to a 0.83dB gain

330 mVpp signal at the final buffer output with high bias  (gain=1.1, 0.8dB) (fxout1)

Assembly

DLS guitar pedal has been mounted on a 1550B enclosure

The figure below shows a bottom view of the Hammond 1550B enclosure open without lid showing the DLS guitar pedal with audio jacks and DC jack, the 3PDT footswitch, the 9V battery

The figure below shows a top view of the Hammond 1550B enclosure showing audio jacks, DC jack, potentiometers, LED, toggle switch and the 3PDT footswitch: