- Main board (from now on DMFX-1-1) is 8-layers on FR4 dielectric (144 x 100mm), green soldermask and white top-bottom silkscreen, inner layer copper thickness is 18 μm (1/2 oz.), outer plated copper layer is 30 um. PCB thickness is 1.55 mm. Outer layers traces are 125μm, inner layer traces 100μm, isolation distances are 100μm. Hole density <1000/dm2. Minimum finished hole is 150μm. This corresponds to Eurocircuits pattern class 8 drill class D.
- Mezzanine board (from now on DMFX-1-2) is 2-layers on FR4 dielectric (100 x 68mm). green soldermask, and white top silkscreen, layer plated copper thickness is 35μm. PCB thickness is 1.55mm. Minimum trace width is 250μm and minimu isolation distance is 250 μm. Minimum finished hole is 350μm. This corresponds to Eurocircuits pattern class 3, drill class B.
Here you can verify
Eurocircuits pattern classification.
DMFX-1-1 requires a quite high and therefore more expensive pattern and drill class (
8D)
The main reason for that is that DSPs are 144-pin
0.8 mm pitch BGA devices. The main challenge of this project is using those tiny BGAs with 0.8 mm pitch which are not very well suited for a DIY application, and the biggest challenge of all is manually soldering those BGAs
But 0.8 mm pitch BGAs also impose constraints on minimum trace width and the number of layers to be able to fanout all the BGA pins.
If minimum finished plated drill (PTH) size is 150μm for class D, minimum production hole diameter (PHD) size is 250μm and minimum inner/outer annular ring (IAR/OAR) is 100μm, which corresponds to a via pad size of 450μm (PTH + 2xOAR/IAR = 250+100+100)
That means that between two 450μm vias spaced 800μm there is a distance of 350μm within which we have to pass fanout traces, class 7 requires 125μm traces an isolation and hence 3x125μm=375μm. Conclusion: a
class 8D is required with
minimum trace width 125μm and minimum isolation of 100μm.
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| DMFX-1-1: PCB design rules |
There are four signal layers: top, bottom and internal layers 3 and 4, but all signal layers include ground planes (analog and digital), this helps copper balancing on PCB but also it helps to shield and reduce noise if some via stitching is added so that good ground connection is assured on all layers.
Layer 3 uses mainly horizontal routing and layer 4 uses vertical routing.
Layers 2 and 5 are mainly ground and power planes.
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| DMFX-1-1: Top layer - layer 1 (signals) |
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| DMFX-1-1: Layer 3 (signals, horizontal routing) |
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DMFX-1-1: Layer 4 (signals, vertical routing)
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| DMFX-1-1: Layer 5 (Power planes) |
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| DMFX-1-1: Bottom layer - layer 6 (signals) |
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| DMFX-1-1: Assembly top |
Notes:
It is recommended to move capacitor C180 down as indicated by the red arrow in the following figure, below the line marked by the green arrow that shows the position of the border of the mezzanine board. C180 electrolytic capacitor is too high and mezzanine board may not be fully plugged in.
